A Novel Net Weighting Algorithm for Power and Timing-Driven Placement
نویسندگان
چکیده
منابع مشابه
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing based placement has minimized area, but with deep submicron design, minimizing wirelength delay is also needed. The algorithm discussed in this paper is the first parallel algorithm for timing driven placement. We have us...
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2018
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2018/3905967